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Design Exploration of Hardware Accelerators For The K-NN Algorithm

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dc.contributor.advisor Shawki Areibi, Gary Grewal
dc.contributor.author Jamma, Dunia
dc.date.accessioned 2016-09-08T17:10:15Z
dc.date.available 2016-09-08T17:10:15Z
dc.date.copyright 2016-08
dc.date.created 2016-08-01
dc.date.issued 2016-09-08
dc.identifier.uri http://hdl.handle.net/10214/9994
dc.description.abstract Increasingly, machine-learning algorithms are playing an important role in the context of embedded and real-time systems. Applications such as wireless sensor networks, security, and commercial enterprises rely increasingly on machine-learning algorithms to efficiently make pre- dictive decisions based on the large volumes of data these systems collect. Most supervised machine-learning algorithms, however, require relatively large amounts of runtime to perform training and/or classification due to the size and dimensionality of the data they must work with. Therefore, there is a need to accelerate the runtime of these algorithms, especially for real-time applications. In this thesis, several different hardware accelerators are proposed and compared for the K-Nearest Neighbor (K-NN) classification algorithm. These accelerators are developed using Xilinx Vivado High-Level Synthesis (HLS) and Cadence Tensilica tools, and represent different (tightly coupled versus semi-tightly coupled) architectures. The experimental results, based on several benchmarks, show that hardware speedups for an HLS range from 48x-168x, while those obtained using Cadence Tensilica tools range from 86x-650x. en_US
dc.language.iso en en_US
dc.subject Design exploration en_US
dc.subject K-NN en_US
dc.subject FPGAs en_US
dc.subject ASIP en_US
dc.subject HLS en_US
dc.title Design Exploration of Hardware Accelerators For The K-NN Algorithm en_US
dc.type Thesis en_US
dc.degree.programme Engineering en_US
dc.degree.name Master of Applied Science en_US
dc.degree.department School of Engineering en_US
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