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Real-Time Operating System Hardware Extension Core for System-on-Chip Designs

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dc.contributor.advisor Muresan, Radu
dc.contributor.advisor Gardner, William
dc.contributor.author Best, Joel
dc.date.accessioned 2013-01-08T19:11:35Z
dc.date.available 2013-01-08T19:11:35Z
dc.date.copyright 2013-01
dc.date.created 2013-01-04
dc.date.issued 2013-01-08
dc.identifier.uri http://hdl.handle.net/10214/5257
dc.description.abstract This thesis presents a real-time operating system hardware extension core which supports the integration of hardware accelerators into real-time system-on-chip designs as hardware tasks. The hardware extension core utilizes reconfigurable logic to manage synchronization events, data transfers, and hardware task control. A reduction in interrupt latency, frequency, and execution time provides performance and predictability improvements for real-time applications. Required communication between the CPU and hardware accelerators is also reduced significantly. Compared to a software implementation, synthetic benchmarks of common synchronization tasks show up to a 41% increase in synchronization performance. Analysis of a test case design for audio encoding and encryption using three hardware accelerators shows results of a 2.89x throughput improvement in comparison to the use of software device driver tasks. Overall, this design simplifies the integration of hardware accelerators into real-time system-on-chip designs while improving the performance and predictability of these systems. en_US
dc.language.iso en en_US
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/2.5/ca/ *
dc.subject Real-Time Systems en_US
dc.subject System-on-Chip en_US
dc.subject Hardware Accelerators en_US
dc.subject Reconfigurable Logic en_US
dc.title Real-Time Operating System Hardware Extension Core for System-on-Chip Designs en_US
dc.type Thesis en_US
dc.degree.programme Engineering en_US
dc.degree.name Master of Applied Science en_US
dc.degree.department School of Engineering en_US
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