An Analytical Timing Driven Placement Tool for Heterogeneous FPGA Architectures

Abstract

Field Programmable Gate Arrays (FPGAs) are reconfigurable integrated circuits which can provide fast computing power to an application without the need for specialized hardware. Placement is a challenging and time-consuming step in the Computer-Aided Design (CAD) process of configuring an FPGA. In this thesis we develop a novel timing-driven analytic placer without explicit packing for Xilinx UltraScale FPGA devices called GPlace4.0. Our placement algorithms simultaneously optimizes for the conflicting objectives of wirelength, timing and routability throughout the flow. We evaluate the effectiveness of our placer on the ISPD 2016 benchmark suite as well as on industrial benchmarks. Experimental results show that on average, GPlace4.0 achieves an 8% increase in maximum clock frequency over the Xilinx Vivado 2018.1 placer while at the same time producing placements with 18% lower routed wirelength. We also achieve high routability with placements that require 80% less time to route than those produced by Vivado.