Coprocessor architecture with scaled dynamic switching activity for embedded cryptosystems

dc.contributor.advisorMuresan, Radu
dc.contributor.authorXu, Leijian of Engineeringen_US of Guelphen_US of Scienceen_US
dc.description.abstractWith the increasing security requirements for embedded systems, security has grown into a new metric dimension in the design process of embedded cryptosystems, where there is the potential for sensitive information leaks via timing, power, and electromagnetic side-channels. Since power consumption relates to data and instruction dependency, power analysis attacks are the most powerful attacks in modern cryptanalysis. This thesis introduces a new architecture for cryptographic processors that supports the dynamic scaling of the switching activity in order to regulate its power and current consumption to a fixed pre-programmed level as a countermeasure against power analysis attacks and other side-channel attacks. Using CMOSP18 technology and the VHDL hardware language to implement the architecture, the simulation results based on the Synopsys NANOSIM show that the current consumption of a processor can be controlled in real-time, thus making it possible for this technique to be used as a hardware countermeasure against power analysis attacks.en_US
dc.publisherUniversity of Guelphen_US
dc.rights.licenseAll items in the Atrium are protected by copyright with all rights reserved unless otherwise indicated.
dc.subjectembedded systemsen_US
dc.subjectembedded cryptosystemsen_US
dc.subjectsensitive informationen_US
dc.subjectpower analysis attacksen_US
dc.subjectcryptographic processorsen_US
dc.subjectdynamic scalingen_US
dc.subjectswitching activityen_US
dc.titleCoprocessor architecture with scaled dynamic switching activity for embedded cryptosystemsen_US


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