Coprocessor architecture with scaled dynamic switching activity for embedded cryptosystems
With the increasing security requirements for embedded systems, security has grown into a new metric dimension in the design process of embedded cryptosystems, where there is the potential for sensitive information leaks via timing, power, and electromagnetic side-channels. Since power consumption relates to data and instruction dependency, power analysis attacks are the most powerful attacks in modern cryptanalysis. This thesis introduces a new architecture for cryptographic processors that supports the dynamic scaling of the switching activity in order to regulate its power and current consumption to a fixed pre-programmed level as a countermeasure against power analysis attacks and other side-channel attacks. Using CMOSP18 technology and the VHDL hardware language to implement the architecture, the simulation results based on the Synopsys NANOSIM show that the current consumption of a processor can be controlled in real-time, thus making it possible for this technique to be used as a hardware countermeasure against power analysis attacks.