This thesis investigates the design trade-offs and methods of implementing charge reuse in switched-capacitor power converters resulting in improved power conversion efficiency. A detailed analysis of the process of charge reuse and its relation with power savings is included. The use of an auxiliary capacitor bank structure for improving efficiency is investigated, and the resulting design trade-offs are explored. A dual-access capacitor bank circuit is presented, which results in a factor of four reduction in the capacitor bank area, at no cost to the designer. The capacitor bank structure is simulated and verified using a voltage doubler designed in 65 nm integration technology. The results of the simulations show a peak power conversion efficiency of 90%, which indicates a 5% improvement when compared to a conventional voltage doubler without charge reuse. Lastly, in order to address the timing constraints associated with charge reuse, a dynamic biasing method is proposed. The dynamic biasing technique results in a decreased on resistance of the switches, and the simulations indicate that the equalization time can be reduced by as much as a factor of 20. All of the proposed techniques combine to make reducing the dynamic losses on parasitic capacitors simple and well modelled, while resulting in improved performance.