The Integration of Machine Learning Probes and Frameworks into the FPGA CAD Flow

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University of Guelph

Placement and routing are two of the most challenging and time-consuming stages in the Field Programmable Gate Array (FPGA) design flow. Traditional Computer-Aided Design (CAD) tools for FPGAs encounter long compile times and failure to achieve design closure on the large, complex circuits frequently found in modern designs. Recently, Machine Learning (ML) methods have drawn the attention of researchers for their ability to leverage data towards finding efficient solutions to the difficult types of problems encountered in FPGA CAD. In this thesis we propose seven novel ML frameworks to improve the performance of challenging placement and routing tasks. The first three methods we call smart probes due to their ability to accurately predict properties of the final routed solution during placement. We show how these frameworks can provide valuable information to designers early in the CAD flow. A wire delay probe is proposed to improve delay estimates during placement, reducing the minimum critical path delay by 11%. Intermediate placements are predicted to be routable with 97.7% accuracy by the second probe. A collection of probes are added to VTR enabling the minimum channel width to be determined 21× faster and 85% of routing time to be saved. We propose two methods for a sequential decision-making placement frameworks. An ML controller selectively chooses which optimization algorithms to run based on the unique properties of the circuit. Results indicate that the dynamic placement approaches are able to outperform static placement methods with 2.84% lower wirelength and 17% lower runtime, respectively. The final two approaches show how routing time can be reduced by first forecasting the congestion on each routing resource and then using it to initialize their costs within the routing algorithm. We first demonstrate how this can speed up routing using a traditional ML prediction model and then show that performance can be improved further on large circuits using a deep-learning image-to-image framework. Routing time is reduced by 17%-44% without deteriorating solution quality.

FPGA, Machine Learning, Placement, Routing, EDA
T. Martin, G. Grewal and S. Areibi, "A Machine Learning Approach to Predict Timing Delays During FPGA Placement," 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Portland, OR, USA, 2021, pp. 124-127, doi: 10.1109/IPDPSW52791.2021.00026.
T. Martin, S. Areibi and G. Grewal, "Effective Machine-Learning Models for Predicting Routability During FPGA Placement," 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), Raleigh, NC, USA, 2021, pp. 1-6, doi: 10.1109/MLCAD52597.2021.9531243.
T. Martin, C. Barnes, G. Grewal, and S. Areibi, "Integrating machine-learning probes in fpga cad: Why and how?" IEEE Design & Test, vol. 40, no. 5, pp. 7-14, 2023. doi: 10.1109/MDAT.2023.3286334.
T. Martin, C. Barnes, S. Areibi and G. Grewal, "An Adaptive Sequential Decision Making Flow for FPGAs using Machine Learning," 2022 International Conference on Microelectronics (ICM), Casablanca, Morocco, 2022, pp. 34-37, doi: 10.1109/ICM56065.2022.10005468.
U. Siddiqi, T. Martin, S. Van Den Eijnden, A. Shamli, G. Grewal, S. Sait and S. Areibi, "Faster FPGA Routing by Forecasting and Pre-Loading Congestion Information," 2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD), UT, USA, 2022, pp. 15-20, doi: 10.1109/MLCAD55463.2022.9900091