Enhancing FPGA Placement Quality via Machine Learning
Placement is one of the most important steps in the Field Programmable Gate Array(FPGA) design flow. However, placement is an NP-hard problem and time-consuming, therefore attempting to solve it results in poor solutions. To address these issues, machine learning models were developed and integrated into GPlace3.0, an FPGA placer. A convolutional encoder-decoder model for congestion management, DLManage, takes congestion heatmaps as inputs and determines the amount of virtual inflation that should be applied to different modules to manage and mitigate congestion. This model, alongside a congestion estimation model, MLCong, and a routability prediction model, DLRoute, were able to reduce the runtime of GPlace3.0 by 48% without resulting in a decrease in quality. Additionally, DLRoute is further extended to address its poor performance on a class of congestion heatmaps. By splitting DLRoute into two separate models and adding new data, the misclassiffcation rate of DLRoute on congestion heatmaps from phase III of GPlace3.0 decreases from 32.56% to 10.47%.