Triple-DES ASIC implementation for the current flattening support architecture
As a powerful and successful cryptanalytic technique, power analysis attacks (PAA) has become one of the major concern in an embedded cryptosystem design. PAA base their success in CMOS devices on power to data dependency. The magnitude of this dependency can be reduced by low-power design techniques and thus the success of PAA could be diminished. The thesis investigates novel pipeline architecture of the Triple-DES (3-DES) algorithm using an ASIC technology and is implemented in CMOSP18 process. This thesis presents simulation and synthesis results of the 3-DES module. The synthesis results show that the proposed 3-DES block is power and area efficient and offers less gate complexity compared to the previously reported 3-DES implementations. The 3-DES block is also simulated at a block-level using Nanosim tool to examine the power to data dependency magnitude. Other results presented include average current and power consumptions of the 3-DES module using a block-level approach. This research is important, since to our knowledge, this is the first time low-power 3-DES module has been developed in CMOSP18 technology.