Embedded image feature extraction system on a single FPGA chip
The motivation behind this research is to develop a prototype system of real-time corner detection for portable multimedia devices. A number of corner detection algorithms were analyzed. The advantages and disadvantages of each algorithm were identified. The Plessy algorithm was found to have good stability, accuracy, significantly better performance in natural images and was the most appropriate algorithm for hardware implementation. To overcome the weakness of the board-based designs, the Plessy algorithm was implemented on a single FPGA chip by using a hardware/software co-design of the embedded system. This approach aims to take advantage of the high performance of FPGAs and the flexibility of the processor(s). The results show that this prototype system can achieve more than 3 times throughput than previous board-based designs. The input of this system is a gray level image with a high bandwidth and the output is a set of image corner locations with a low bandwidth. The hardware and software can be processed in parallel and also can be modified or replaced rapidly and conveniently.