A reconfigurable hardware implementation of genetic algorithms for VLSI CAD design
The use of integrated circuits in high-performance computing and consumer electronics has been growing at a very fast pace. Due to increasing complexity of VLSI circuits, there is a growing need for efficient CAD tools. Partitioning is a technique, widely used to solve diverse problems occurring in VLSI CAD. A Genetic Algorithm (GA) is a robust problem solving method which can be used for solving a wide range of problems, including the problem of circuit partitioning. Although, a GA can provide very good solutions for circuit partitioning, the amount of computations and iterations required for this method is enormous. As a result, software implementations of GA can become extremely slow. An emerging technology capable of providing high computational performance is reconfigurable computing. In this research, an architecture for implementing GA on an FPGA is proposed. The design was functionally verified by writing a testbench, simulating it using ModelSim and was synthesized on Virtex part xcv2000e using Xilinx ISE 5.1. The GA processor proposed in this thesis achieves more than 100x improvement in processing speed as compared to the software implementation.