Routability prediction for Field Programmable Gate Arrays with a routing hierarchy

dc.contributor.advisorBanerji, D.K.
dc.contributor.authorDai, Zhibin
dc.date.accessioned2020-08-24T15:54:00Z
dc.date.available2020-08-24T15:54:00Z
dc.date.copyright2000
dc.degree.departmentDepartment of Computing and Information Scienceen_US
dc.degree.grantorUniversity of Guelphen_US
dc.degree.nameMaster of Scienceen_US
dc.description.abstractField Programmable Gate Arrays (FPGAs) have emerged in the last fifteen years as a key technology for implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is routing implementation, which is greatly affected by the routing architecture and routing resources. This thesis explores the effective utilization of a routing hierarchy that can be present in conventional FPGAs as well as in hierarchical FPGAs (HFPGAs). A statistical model is adopted to investigate the routability on both kinds of FPGAs. The performance of our proposed FPGA models is compared to those without a routing hierarchy. Experimental methods are used to determine the flexibility and switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs consumes fewer routing resources and that the speed of designs implemented in the FPGAs can be greatly improved.en_US
dc.identifier.urihttps://hdl.handle.net/10214/20532
dc.language.isoen
dc.publisherUniversity of Guelphen_US
dc.rights.licenseAll items in the Atrium are protected by copyright with all rights reserved unless otherwise indicated.
dc.subjectField Programmable Gate Arraysen_US
dc.subjectdigital circuitsen_US
dc.subjectVLSIen_US
dc.subjectrouting implementationen_US
dc.subjectrouting architectureen_US
dc.subjectrouting resourcesen_US
dc.subjectrouting hierarchyen_US
dc.subjecthierarchical FPGAsen_US
dc.titleRoutability prediction for Field Programmable Gate Arrays with a routing hierarchyen_US
dc.typeThesisen_US

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