Routability prediction for Field Programmable Gate Arrays with a routing hierarchy
Field Programmable Gate Arrays (FPGAs) have emerged in the last fifteen years as a key technology for implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is routing implementation, which is greatly affected by the routing architecture and routing resources. This thesis explores the effective utilization of a routing hierarchy that can be present in conventional FPGAs as well as in hierarchical FPGAs (HFPGAs). A statistical model is adopted to investigate the routability on both kinds of FPGAs. The performance of our proposed FPGA models is compared to those without a routing hierarchy. Experimental methods are used to determine the flexibility and switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs consumes fewer routing resources and that the speed of designs implemented in the FPGAs can be greatly improved.