Management of data movement operations in DSP code generation

Bialecki, Artur
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University of Guelph

"Code generation" for Digital Signal Processors (DSPs) is notoriously difficult because of their heterogeneous register classes, irregular instructions sets, and substantial instruction-level parallelism. Due to the limited number of available registers on DSPs, judicious decisions must be made regarding which program values are to be retained in registers and which must be "spilled" to memory. Values that cannot be retained in registers must be retrieved from memory prior to their use; this requires additional store and load instructions to be inserted into the original code producing longer instruction sequences. The presented optimization algorithm attempts to "spill" variables to memory in such a way as to minimize the number of extra instructions that must be included in the final code. It is combined with a second algorithm which reverses some of the earlier "spills" if possible, to further minimize the number of extra instructions.

Digital Signal Processors, Code generation, Data movement, Register classes, Instruction-level parrallelism