Area/congestion-driven placement for VLSI circuit layout
This thesis presents and compares several global wirelength-driven placement algorithms. Both flat and hierarchical approaches are implemented to find the effectiveness of these approaches. Experiments conducted indicate that the Attractor-Repeller Placer (ARP) method produces the best results and a hierarchical approach can reduce the computation time of ARP by almost 85%. An evolutionary based hybrid algorithm for circuit placement is also presented, where a pure Genetic algorithm is combined with a local search, constructive technique and clustering technique to explore the solution space more effectively. In addition to wirelength optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is also considered in this thesis via a post-processing congestion reduction technique. Results obtained show that the flat congestion-driven placement approach reduces the congestion by about 51% with a slight increase on the wirelength.