Routability prediction for field-programmable gate arrays with mixed routing resources

dc.contributor.advisorBanerji, D.K.
dc.contributor.advisorGrewal, Gary
dc.contributor.authorChen, Jian of Computing and Information Scienceen_US of Guelphen_US of Scienceen_US
dc.description.abstractField Programmable Gate Arrays (FPGAs) have emerged as a key technology for implementing logic circuits as a customized VLSI chip. Much research has been done on their architecture and applications. One particularly important area of study is routing implementation, which is greatly affected by the routing architecture and routing resources. This thesis explores the effective utilization of mixed routing resources that can be present in conventional FPGAs as well as in hierarchical FPGAs (HFPGAs). A statistical model is adopted to investigate the routability on both kinds of FPGAs. The performance of our proposed FPGA models is compared to those without mixed routing resources. Experimental methods are used to determine the flexibility and switch consumption of various routing resources. Results show that integrating mixed routing resources into FPGAs consumes fewer routing resources, therefore, the speed of designs implemented in the FPGAs can be greatly improved, and area-efficiency is enhanced.en_US
dc.publisherUniversity of Guelphen_US
dc.rights.licenseAll items in the Atrium are protected by copyright with all rights reserved unless otherwise indicated.
dc.subjectField Programmable Gate Arraysen_US
dc.subjectlogic circuitsen_US
dc.subjectVLSI chipen_US
dc.subjectrouting implementationen_US
dc.subjectrouting architectureen_US
dc.subjectrouting resourcesen_US
dc.subjectconventional FPGAsen_US
dc.subjecthierarchical FPGAsen_US
dc.subjectswitch consumptionen_US
dc.subjectmixed routing resourcesen_US
dc.titleRoutability prediction for field-programmable gate arrays with mixed routing resourcesen_US


Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
6.77 MB
Adobe Portable Document Format