Routability prediction for field-programmable gate arrays with mixed routing resources
Field Programmable Gate Arrays (FPGAs) have emerged as a key technology for implementing logic circuits as a customized VLSI chip. Much research has been done on their architecture and applications. One particularly important area of study is routing implementation, which is greatly affected by the routing architecture and routing resources. This thesis explores the effective utilization of mixed routing resources that can be present in conventional FPGAs as well as in hierarchical FPGAs (HFPGAs). A statistical model is adopted to investigate the routability on both kinds of FPGAs. The performance of our proposed FPGA models is compared to those without mixed routing resources. Experimental methods are used to determine the flexibility and switch consumption of various routing resources. Results show that integrating mixed routing resources into FPGAs consumes fewer routing resources, therefore, the speed of designs implemented in the FPGAs can be greatly improved, and area-efficiency is enhanced.